? semiconductor components industries, llc, 2015 february, 2017 ? rev. 2 1 publication order number: nvmfs5c404n/d nvmfs5c404n power mosfet 40 v, 0.7 m , 378 a, single n ? channel features ? small footprint (5x6 mm) for compact design ? low r ds(on) to minimize conduction losses ? low q g and capacitance to minimize driver losses ? nvmfs5c404nwf ? wettable flank option for enhanced optical inspection ? aec ? q101 qualified and ppap capable ? these devices are pb ? free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 40 v gate ? to ? source voltage v gs 20 v continuous drain current r jc (notes 1, 3) steady state t c = 25 c i d 378 a t c = 100 c 267 power dissipation r jc (note 1) t c = 25 c p d 200 w t c = 100 c 100 continuous drain current r ja (notes 1, 2, 3) steady state t a = 25 c i d 53 a t a = 100 c 37 power dissipation r ja (notes 1 & 2) t a = 25 c p d 3.9 w t a = 100 c 1.9 pulsed drain current t a = 25 c, t p = 10 s i dm 900 a operating junction and storage temperature t j , t stg ? 55 to + 175 c source current (body diode) i s 191 a single pulse drain ? to ? source avalanche energy (i l(pk) = 38 a) e as 907 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. thermal resistance maximum ratings parameter symbol value unit junction ? to ? case ? steady state r jc 0.75 c/w junction ? to ? ambient ? steady state (note 2) r ja 39 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 3. maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. marking diagram www. onsemi.com xxxxxx aywzz v (br)dss r ds(on) max i d max 40 v 0.7 m @ 10 v 378 a g (4) s (1,2,3) n ? channel mosfet d (5,6) s s s g d d d d dfn5 (so ? 8fl) case 488aa style 1 1 see detailed ordering, marking and shipping information in the package dimensions section on p age 5 of this data sheet. ordering information xxxxxx = 5c404n xxxxxx = (nvmfs5c404n) or xxxxxx = 404nwf xxxxxx = (nvmfs5c404nwf) a = assembly location y = year w = work week zz = lot traceability
nvmfs5c404n www. onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 40 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss / t j 19.7 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 40 v t j = 25 c 10 a t j = 125 c 250 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 4) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 2.0 4.0 v threshold temperature coefficient v gs(th) /t j ? 6.2 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v i d = 50 a 0.57 0.7 m forward transconductance g fs v ds =15 v, i d = 50 a 210 s charges, capacitances & gate resistance input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 25 v 8400 pf output capacitance c oss 4600 reverse transfer capacitance c rss 120 total gate charge q g(tot) v gs = 10 v, v ds = 20 v; i d = 50 a 128 nc threshold gate charge q g(th) v gs = 10 v, v ds = 20 v; i d = 50 a 22 gate ? to ? source charge q gs 35 gate ? to ? drain charge q gd 26 plateau voltage v gp 4.3 v switching characteristics (note 5) turn ? on delay time t d(on) v gs = 10 v, v ds = 20 v, i d = 50 a, r g = 2.5 16 ns rise time t r 113 turn ? off delay time t d(off) 77 fall time t f 109 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 50 a t j = 25 c 0.76 1.2 v t j = 125 c 0.63 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = 50 a 96 ns charge time t a 49 discharge time t b 47 reverse recovery charge q rr 189 nc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. pulse test: pulse width 300 s, duty cycle 2%. 5. switching characteristics are independent of operating junction temperatures.
nvmfs5c404n www. onsemi.com 3 typical characteristics 5.6 v 5.4 v 5.2 v 5.0 v 4.8 v 4.6 v figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 3.0 1.5 1.0 0.5 0 0 100 200 300 400 500 5.0 4.0 3.0 0 100 200 300 400 figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage v gs , gate voltage (v) i d , drain current (a) 10 9 8 7 6 5 4 3 0.0 1.0 2.0 4.0 500 700 400 200 100 0 0.50 0.52 0.60 0.64 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 150 125 100 75 25 0 ? 25 ? 50 0.7 0.9 1.1 1.3 1.5 1.7 1.9 40 35 30 25 15 5 1.e ? 07 1.e ? 04 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance (m ) r ds(on) , drain ? to ? source resistance (m ) r ds(on) , normalized drain ? to ? source resistance i dss , leakage (a) 5.8 v 6.5 v t j = 125 c t j = 25 c t j = ? 55 c t j = 25 c i ds = 25 a v gs = 10 v i d = 50 a 50 175 t j = 125 c t j = 85 c 600 700 500 600 2.0 2.5 3.0 0.5 1.5 2.5 4.5 3.5 0.54 1.e ? 06 1.e ? 05 1.e ? 03 10 20 t j = 150 c 6.0 300 600 800 0.56 0.58 0.62 0 800 10 v 8 v 7 v 6 v 4.4 v 2.1 v ds = 10 v
nvmfs5c404n www. onsemi.com 4 typical characteristics figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 40 30 20 10 0 1e+0 1e+1 1e+3 90 70 50 40 20 10 0 0 2 4 6 8 10 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 1000 0.9 0.8 1.0 0.7 0.6 0.5 0.4 0.3 1 50 figure 11. safe operating area figure 12. i peak vs. time in avalanche v ds , drain ? to ? source voltage (v) time in avalanche (s) 100 10 1 0.1 1 10 100 1000 1 10 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i ds , drain ? to ? source current (a) i peak (a) v gs = 0 v t j = 25 c f = 1 mhz c iss c oss c rss v ds = 20 v i d = 50 a t j = 25 c q t q gs q gd v gs = 10 v v ds = 20 v i d = 50 a t d(off) t d(on) t f t r t j = 150 c t j = 25 c t j = ? 55 c t j(initial) = 100 c t j(initial) = 25 c 1e ? 04 1e ? 02 r ds(on) limit thermal limit package limit dc 0.01 ms 0.1 ms 1 ms 10 ms t c = 25 c v gs 10 v 1e+2 1e+4 1e ? 03 1000 35 25 15 5 1e+5 30 60 t j = 125 c 5 10 100 80 130 110 100 120
nvmfs5c404n www. onsemi.com 5 figure 13. thermal characteristics pulse time (sec) 1e ? 02 1e ? 03 1e+00 1e ? 04 1e ? 01 1e ? 05 1e+01 1e ? 06 0.01 0.1 1 10 100 r ja (t) ( c/w) 1e+02 1e+03 single pulse 50% duty cycle 20% 10% 5% 2% 1% nvmfs5c404n 650 mm 2 , 2 oz., cu single layer pad device ordering information device marking package shipping ? nvmfs5c404nt1g 5c404n dfn5 (pb ? free) 1500 / tape & reel nvmfs5c404nwft1g 404nwf dfn5 (pb ? free, wettable flanks) 1500 / tape & reel NVMFS5C404NT3G 5c404n dfn5 (pb ? free) 5000 / tape & reel nvmfs5c404nwft3g 404nwf dfn5 (pb ? free, wettable flanks) 5000 / tape & reel nvmfs5c404naft1g 5c404 dfn5 (pb ? free) 1500 / tape & reel nvmfs5c404nwfaft1g 404nwf dfn5 (pb ? free, wettable flanks) 1500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nvmfs5c404n www. onsemi.com 6 package dimensions m 3.00 3.40 0 ??? 3.80 12 dfn5 5x6, 1.27p (so ? 8fl) case 488aa issue m notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 top view side view bottom view d1 e1 d e 2 2 b a 0.20 c 0.20 c 2 x 2 x dim min nom millimeters a 0.90 1.00 a1 0.00 ??? b 0.33 0.41 c 0.23 0.28 d 5.15 d1 4.70 4.90 d2 3.80 4.00 e 6.15 e1 5.70 5.90 e2 3.45 3.65 e 1.27 bsc g 0.51 0.575 k 1.20 1.35 l 0.51 0.575 l1 0.125 ref a 0.10 c 0.10 c detail a 14 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 c 4 x c seating plane max 1.10 0.05 0.51 0.33 5.10 4.20 6.10 3.85 0.71 1.50 0.71 style 1: pin 1. source 2. source 3. source 4. gate 5. drain m *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.270 2x 0.750 1.000 0.905 4.530 1.530 4.560 0.495 3.200 1.330 0.965 2x 2x 4x 4x pin 5 (exposed pad) 5.00 5.30 6.00 6.30 pitch dimensions: millimeters 1 recommended e on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nvmfs5c404n/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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